1. Field of the Invention
This invention relates generally to a nonvolatile memory circuits, devices, and methods of operation. More particularly, this invention relates to floating gate tunneling oxide (FLOTOX) electrically erasable programmable read only memory EEPROM circuits, devices, and method of operation.
2. Description of Related Art
“A 16 Kb Electrically Erasable Nonvolatile Memory” Johnson, et al., Digest of Technical Papers 1980 IEEE International Solid-State Circuits Conference, February 1980, Volume: XXIII, pp: 152-153 describes an electrically erasable nonvolatile memory using a Floating Gate Tunnel Oxide (FLOTOX) two-transistor cell. The cell size was 0.85 mil2 using 3.5 μm technology. Tunnel oxide thickness was less than 200 Angstrom, and endurance of more than 105 cycles. This cell and the design techniques were widely adopted by the industry on many other memories.
Referring to FIGS. 1a-1c, a two-transistor FLOTOX EEPROM cell structure 5 has a single polycrystalline select transistor ST and a double polycrystalline floating-gate transistor FT. The two-transistor FLOTOX EEPROM cell structure 5 is formed on a P-type substrate 10. An N-type impurity is diffused into the surface of the P-type substrate 10 to form the N+ drain 15 of the select transistor ST, the merged N+ source/drain 20 of the select transistor ST and the floating gate transistor FT, and the source 25 of the floating gate transistor FT. A silicon oxide layer is formed over the surface of the P-type substrate 10. In an area over the floating gate transistor FT region of the merged N+ source/drain 20, the silicon oxide layer is thinned to form the thin oxide region 50 of the floating gate transistor FT. A first polycrystalline silicon layer is formed on top of the silicon oxide layer generally in the region of the thin oxide region 50 to form the floating gate 50 of the floating gate transistor FT. The area of the silicon oxide layer essentially between the N+ drain 15 and the merged N+ source/drain 20 and the area of the silicon oxide layer between the merged N+ source/drain 20 and the source 25 form the thick oxide regions 35 and 55, respectively. A second polycrystalline layer is formed over the thick oxide region 35 between the N+ drain 15 and the merged N+ source/drain 20 to form the gate 30 of the select transistor ST. The second polycrystalline layer is also formed on top of the thick oxide region 55 and the first polycrystalline silicon layer 50 to form the control gate of the floating gate transistor FT.
The N+ drain 15 of the select transistor ST is connected to a bit line BL and the gate of the select transistor ST is connected to a select word line SWL. The source 25 of the floating gate transistor FT is connected to a source line SL. The control gate 40 of the floating gate transistor FT is connected to a gated word line GWL.
The two-transistor FLOTOX EEPROM cell structure 5 is in reality a three device cell. The floating gate transistor FT is the merging of a floating gate charge storage device FGD with a second switching device ST2, as shown in FIG. 1b. The gate of the switching device ST2 may be a single polycrystalline structure formed of the first level polycrystalline silicon layer (not shown), the second poly crystalline layer 40, or a shorted second of the first and second polycrystalline layers (not shown).
The select transistor ST1 is a high-voltage high voltage enhancement-mode NMOS device designed to sustain a very large programming voltage level (approximately 16V) applied to the bit line during programming. The select transistors ST1 and ST2 are structured on each side of the floating gate charge storage device to prevent high voltage disturbance or punch-through of the floating gate charge storage device FGD during the program operation.
One of the most important features of two-transistor FLOTOX EEPROM cell structure 5 is that it is designed to use the single polarity of positive high-voltage power supply voltage source of approximately 16V to perform both program and erase operations. Thus a much simplified process to manufacture both two-transistor FLOTOX EEPROM cell structure 5 and the associated peripheral devices. The structure eliminates any requirement for any triple-P-well within the deep N-well process steps for forming both two-transistor FLOTOX EEPROM cell structures 5 and the associate high voltage and low voltage devices in peripheral area. A second feature of two-transistor FLOTOX EEPROM cell structure 5 is to adopt the low-current Fowler-Nordheim tunneling phenomenon to perform channel-erase and channel-program. A third feature of the two-transistor FLOTOX EEPROM cell structure 5 is that it permits a unique array architecture, which is capable of organizing the two-transistor FLOTOX EEPROM cell structures 5 into alterable units of multiple cell structures such as nibbles (4 bits), bytes, half-word, words, etc. This capability provides the well-known super endurance cycle performance. Currently, all two-transistor FLOTOX EEPROM cell structure 5 designs can meet the application specification of an extremely high-changing rate of 1 million cycles in unit of byte-data.
A major drawback of the two-transistor FLOTOX EEPROM cell structure 5 is that it requires a large programming voltage (approximately 16V) in the channel region 60 between merged N+ source/drain 20 and source 25 with respect to the control gate 40 that has the ground reference voltage level (0V) applied to it. This allows the successful initiation of the Fowler Nordheim channel program. The very large programming voltage level must be approximately 16V in two-transistor FLOTOX EEPROM cell structure's 5 channel 40 build up a sufficiently large voltage field in the tunneling oxide layer 50 between the floating-gate layer 45 and two-transistor FLOTOX EEPROM cell structure's 5 channel region 60 to initiate the Fowler-Nordheim tunneling. The very large programming voltage level induces the Fowler-Nordheim tunneling effect to extract the electrons out of cell's floating-gate 45 to P-substrate 10 in the channel region 60. The very large programming voltage level in channel region 60 is coupled from the bit line BL through the select transistor ST associated with the corresponding floating-gate transistor FT. For each of the unselected two-transistor FLOTOX EEPROM cell structures 5 connected to the same bit line BL, the length of the channel 65 of the select transistor ST has to be kept sufficiently long to prevent the punch-through when the very large programming voltage level is applied across the channel region 65 between select transistor's ST N+ drain 15 and the merged N+ source/drain 20 during the program operation. As a result of requiring the very large programming voltage level in the two-transistor FLOTOX EEPROM cell structure's 5 channel region 65, the cell size even in the present day designs is still very big and un-scalable. The most advanced two-transistor FLOTOX EEPROM cell 5 technology suitable for economic production stays above 0.13 μm minimum feature in 2009 without foreseeing a practical scaling beyond 0.13 μm in the future.
FIG. 2 is a schematic diagram of a portion of an array 100 of two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h and 115a, 115b, . . . , 115h showing two byte-alterable units 105a and 105b. Each of the two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h and 115a, 115b, . . . , 115h is formed of a select transistor ST and a floating gate transistor FT that is formed and functions as described above in FIGS. 1a, 1b, and 1c. The drains of the select transistors ST of the two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h and 115a, 115b, . . . , 115h are connected to the bit lines BL0, BL1, . . . , BL7. The two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h and 115a, 115b, . . . , 115h that are arranged column-wise are commonly connected to an associated bit line BL0, BL1, . . . , BL7. The sources of the floating gate transistors FT of all the two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h and 115a, 115b, . . . , 115h are connected to a common source line SL0. In many implementations of the arrays of the two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h and 115a, 115b, . . . , 115h, the common source line SL0 is connected to the ground reference voltage level. As structured, the common source line SL0 is placed parallel to the word lines WL0 and WL1 and essentially connects the every two-transistor FLOTOX EEPROM cell 110a, 110b, . . . , 110h and 115a, 115b, . . . , 115h of the array 100 into an integrated unit.
The word line WL0 is connected to the gates of the select transistors ST of the two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h of the byte-alterable unit 105a. The word line WL1 is connected to the gates of the select transistors ST of the two-transistor FLOTOX EEPROM cells 115a, 115b, . . . , 115h of the byte-alterable unit 105b. Each of the byte-alterable units 105a and 105b further includes a gated bit line select transistor GBLT0 and GBLT1. The gate of the gated bit line select transistor GBLT0 is connected to the word line WL0 and the gate of the gated bit line select transistor GBLT1 is connected to the word line WL1. The drains of the gated bit line select transistor GBLT0 and GBLT1 are connected to the gated bit line BYTEL. The sources of the gated bit line select transistor GBLT0 and GBLT1 are connected to the control gates of the floating gate transistors FT of the respective byte-alterable units 105a and 105b. 
FIGS. 3a and 3b are tables of the biasing voltages for operating a FLOTOX EEPROM memory device. The table of FIG. 3a illustrates the biasing voltages applied to the bit lines BL, source lines SL, word lines BL, and gated word lines through the gated bit line select transistor GBLT0 or GBLT1 from the gated bit line BYTEL for the selected two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h or 115a, 115b, . . . , 115h that are selected to be read, erased, or programmed. The table of FIG. 3b illustrates the biasing voltages applied to the bit lines BL, source lines SL, word lines BL, and gated word lines through the gated bit line select transistor GBLT0 or GBLT1 from the gated bit line BYTEL for the selected two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h or 115a, 115b, . . . , 115h that are unselected from being read, erased, or programmed.
For those unselected two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h or 115a, 115b, . . . , 115h on the same column and connected to the same bit lines BL0, BL1, . . . , BL7 as the selected two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h or 115a, 115b, . . . , 115h, the channel length of the select transistors ST has to be of a sufficient magnitude to prevent punch-through with the very large programming voltage (HV) developed across over the channel region between the drain and source of the select transistors ST of the unselected two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h or 115a, 115b, . . . , 115h during the program operation. As a result of requiring the very large programming voltage in the channel region of the select transistors ST of the unselected two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h or 115a, 115b, . . . , 115h, the size of the two-transistor FLOTOX EEPROM cells 110a, 110b, . . . , 110h or 115a, 115b, . . . , 115h is still very large and is not scalable.
What is needed is a reliable and scalable two-transistor FLOTOX EEPROM cell structure and array structure beyond the 0.13 μm technology processing size that achieves 1 million endurance cycles, while preventing high voltage disturbance or punch-through.